Cad, PLC, ICs and oth.

When I mention about computer aided design (CAD) some of you occasionally admit it concerns component rapid manufacturing electronic automation which covers thing such as computer controlled of conveyor belt and PLC programming. In fact the two are very different in nature.

The domain of CAD is solely within software. To some extent it refers to how software is used helping integrated circuit (IC) designers to design ICs. These software are also sometimes referred to as CAD tools.



At the same time the higher abstraction level stage of the IC design demands ig creativity, while the the bottom level and details part of IC design can be very routine, repetitive, tedious and boring. The CAD tools help the designers in doing the repetitive and tedious tasks.

While in collage, students majoring in electronics learn basic electronic system design using small number of components called gates. Basic system can be construct with less than 10 gates. By their final year, the students will learn how to construct larger system which consists of up to hundreds of gates. This is not how it is done in the real world.

In the real world, a system such as the Intel Pentium 4 chip is constructed from 14 million gates. And with the current trend, it will not be long before we pass the one billion gates (in one chip) mark. This is so much different from what is thought in college. That is why in the real world, IC is design using different method.

On the very high level a system can be described using special languages, called hardware description language (HDL). Two most prominent HDLs are Verilog and VHDL. Verilog is widely used by designers in North America, and VHDL is widely by the european designers.

Instead of designing a system on gates level, using these languages a system is described at a higher level. Then a software is used to translate this high level description into gates level. This process is called synthesis, and the software is referred to as a synthesis tool. One line in HDL can be translated by the synthesis tool into few gates. Synthesis tool is one of the examples of CAD tool.

Even before a design using HDL is processed by a synthesis tool, there are other CAD tools that can be used by the designers to check if their HDL codes follow certain rules and guidelines. These CAD tools are called rule checker software. The HDL design is check again good circuit design guideline in order to catch possible error which can caused circuit failure when it is converted into gates.

Network of connected gates which are synthesized are called net list.There are various verification CAD tools can be used to analyze a net list. The tools can be a static tools which can look at a net list and resolve it functionality mathematically. There are also dynamic tools such as simulators which look at how the circuit behave virtually when it is operating. Simulated input voltages and currents are fed into the net list, and the simulated output is shown to the designer.

Using these verification tools, designers can verify that their design work - at least in controlled simulated environment. Final verification of the actual chip is still needed because the long and intricate manufacturing process can cause problem to a circuit which not counted in during a simulated verification.

Using various CAD tools,such as synthesis tools,rule checkers and verification tools today designers have been able to create a chip which contains multi million gates in it. Other than synthesis, there are also other CAD tools that help designers with other process of an IC design such as layout tools, and timing verification tools.

The trend is to move into high abstraction using higher level language, which is more abstract than the HDLs such as C or C++ programming languages and let the software to do more and more task in generating the gates. Enabling of the use of C or C++ in designing a hardware system is done with the goal that it will convert some of the software engineers become hardware designers.